Dual-slope integrators are widely used in electrical circuits for measuring and display purposes, e.g. to integrate an input signal which may result from a measurement of a physical parameter or to facilitate the display of a physical parameter translated into an integratable electrical signal on an oscilloscope or other recording medium. Such circuits are used in threshold devices to trigger emergency, warning or other indicating outputs and/or to control processes in response to a physical parameter whose value is translatable into the input signal.
It is known to provide a dual-slope integrator with measured-voltage and reference voltage inputs, an integrating resistor/capacitor/operational amplifier, a comparator connected to the integrating amplifier circuitry to monitor the voltage on the integrating condenser, a clock-pulse generator for producing counting pulses and a counter with a given capacity, e.g. N.sub.1, for counting these pulses. Such circuits are also provided with logic networks and gating stages receiving the clock pulses. The gating stage is controlled by the output of the comparator as are the input switches which deliver the measured voltage and the reference voltage to the system. Conventional dual-slope integrators having these circuit elements connected in the manner described, have several significant disadvantages:
Firstly, the comparator connected to the integrator generates, because of its noise, a time-perturbation effect which, as a consequence of the larger band width of the comparator, is greater than the time perturbation effect resulting from the integration noise, thereby multiplying the effect of transience.
Secondly, the technologically reliable band width and amplification product of the comparator, because of the limited rise velocity of the signal at its input, results in a delay of the comparator signal of up to several microseconds. This transmission delay is highly temperature dependent and has poor long-term stability. It limits the resolution to values less than 10.sup.4 with 2 milliseconds integration time.
Thirdly, because of parasitic capacitances, the integrator output signal has sharp peaks superimposed thereon at the flanks of the clock pulses to produce a faulty response of the comparator.
Fourthly, the two field-effect transistor-input switches, which first apply the input voltage and then the reference voltage to the integrator, naturally generate parasitic charge surges during their switching operations. These surges cannot be effectively compensated within a measuring cycle where three switchovers are effected up to a cutoff of the pulse counter.
Finally, the switching times of the field-effect transistor-input switches of about 1 microsecond are temperature dependent and of poor long-term stability. These switching times limit, as does the comparator delay, the upper limit of the resolution capability and the lower limit of the measuring time.